Terepac’s technology introduces a truly revolutionary advance into the assembly and packaging of microelectronics, by making it possible to enjoy the benefits of ultra low-cost digital electronics in small packages as well as in the more traditional forms of computers, smart phones and similar items. In essence, the process liberates transistors from their wafer-sized cages, making it possible for them to permeate the world with digital intelligence.

The extraordinary advances over the past several decades have brought the microelectronics industry to the point where nearly a billion transistors can be put in an area of one square centimeter, at a cost of only a few dollars (or tens of dollars for the largest chips in the latest technology node). By comparison, a processor containing only about 8,000 transistors powered the first widely-used personal computer, suggesting that many modestly complex computing tasks could be accomplished with such a unit. Indeed, microprocessors of that size – such as the venerable Z80 – are extensively used today for machine control and other embedded applications. However, their price does not scale linearly with transistor count, because price is largely a function of two elements: the area of silicon processed, and the cost of packaging. As a result, such small circuits are still too expensive (costing several tens of cents) for pervasive deployment in natural, industrial or consumer environments.

The Z80, if made with 90 nm lithography (far from today’s state of the art, which now approaches 22 nm for the most advanced products) would occupy a 63 micron square. A standard 300mm wafer would contain millions of these microprocessors, and that wafer would cost no more to make than a wafer containing a far smaller number of personal computer microprocessors or memory chips. However, circuits have not been made this way for two reasons: first, it is not possible to cost-effectively handle such small objects in the electronic packaging process, and second, there would not be room for the required input/output connections using currently available techniques of wirebonding or flip-chip soldering.

Photoprinting Circuit Assembly

Terepac overcomes these two critical obstacles with its patented Photoprinting Circuit Assembly™ process, which replaces the mechanical pick and place step in conventional packaging with a photochemical printing process using a proprietary material known as a Digital Release Adhesive (or DRA). This is a photosensitive polymer which decomposes cleanly to gaseous products at a predetermined temperature, which is substantially reduced in the presence of a photogenerated catalyst.

In operation, the DRA is coated onto a flat, transparent plate, which is then used to pick up thinned, diced silicon (or other) components en masse. The DRA is sufficiently sticky to easily adhere to typical bare dice, which in the case of thin silicon are available on a dicing membrane with a release polymer coating. This plate, analogous to a printing plate, is then brought into close proximity to the desired substrate in an alignment apparatus, where the appropriate combination of light and heat cause the DRA under a chosen die to decompose and release the die.

As the motion of the substrate brings the next target location into position, the printing plate is indexed by one period of the component array, and the irradiation/printing process is repeated.

Interconnection

The chip must now be connected to other chips, or to an antenna. This is conveniently done by some variation of direct-write printing of a fluid conductor precursor, such as a silver-filled epoxy or nanoparticle silver suspension. Inkjets, aerosol printers, and various laser-based processes are all well suited to forming short lines of width well under 100 microns down to a few microns under carefully controlled conditions, and the precursors may be cured at temperatures compatible with flexible substrates such as polyesters (and in some cases even silicones).

Comparison to other processes

Terepac’s process dramatically reduces the mechanical complexity as compared to pick and place tooling— the printing plate need only move a very short distance (perhaps hundreds or even tens of microns) in between each printing operation, instead of having to travel out to a source tape each time. Precision alignment is much easier since the array of components is in exactly (to less than a micron) the same relative position on the printing plate as it was on the dicing tape. Mechanical damage is reduced since there is no needle or vacuum nozzle to touch a thin die – indeed, there is no mechanical contact at all except the highly controlled pressure used to effect the transfer from source to printing plate.

Terepac’s process maintains strict positional control over each die at all times, enabling the printing of only known good dice, and allowing for the use of any kind of component on any kind of substrate (not limited to materials which can be etched into specific shapes, for example, nor requiring any preformed cavities on the substrate). It operates at low temperature with a simple optical system. Finally, it is capable of multiple parallel transfers (an array of components instead of just one at a time) if the dimensional stability of the substrate and product specifications allow.

Extension to more complex circuits

Terepac’s Photoprinting Circuit Assembly process is ideally suited to the production of small integrated systems such as wirelessly networked sensors as well as RFID and smart cards, where the product contains only a few relatively simple components. However, it provides a means of handling ultra-thin components with a minimum of mechanical stress at high speed, regardless of size. This process, which “takes the pick out of pick and place”, is expected to be valuable in many areas of microelectronic assembly as the industry progresses to widespread implementation of thin chips and 3-D integration into stacked packages.

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